![]() ![]() At this time, we were still expecting Intel to use a ring-bus topology, and I mentioned before, adding two cores to a ring bus is fairly easy at the expense of peak latency between cores. In the 4x5 grid, we have 18 cores and two sets of memory channels.īack when Skylake-X was announced at Computex, I wrote that we were expecting the LCC silicon to be a 12-core design. Skylake-X only has four memory channels, but leaks have shown that the new Skylake-SP processors have six memory channels by design, so here they are. What we can see is three regular blue/green vertical areas, which means three on each side, for a total of six. So scoot back to that HCC die image, and zoom in on one of those odd looking ‘cores’: However on the left and right are the DRAM controllers, essentially taking up the same area as a core but also using one of the mesh networking links. At the top are the socket links, along with the PCIe root complexes. This is meant to be a pseudo mockup of a theoretical core of n processors using the mesh topology. ![]() But the second piece of information was given through Intel’s mesh announcement. At the time we postulated that given the size of AVX512, this might be where they were. On closer inspection two of the cores were different: on the second column, the top and bottom ‘cores’ did not look like cores. By counting the regular structures, we can see 4x5 arrangement, or rather a 20-core chip. First was the original Skylake-X announcement back at Computex: one of Intel’s slides had an image of the basic floorplan of the HCC silicon to be used for the high core-count Skylake-X processors:Īt the time, we were a bit stumped by this image. Three things come to our aid in discussing the LCC and HCC silicon. If we had a 100x100 core arrangement, the cores in the middle would have big latency to get anywhere near external memory. This lets us make some predictions about how Intel’s silicon is lining up.Ī side-note for discussion. Ideally, an arrangement where x = y is usually the best bet. Adding a pair of cores in a mesh means that you end up with more corners and more edges – not all cores end up ‘equal’ and there can be performance penalties therein. You either have to add a full row or a full column to increase the die count, whereas in a ring it could be straight forward just to add another pair of cores into the ring (which is what happened over the last few generations). The mesh diagrams on the previous page are all presented as rectangles in x*y arrangements. With a mesh, things get a little more rigid. Put the cores in a circle (or overlapping circles) and away you go. ![]() With a ring bus, ultimately the silicon layout of the cores and the interconnects can be regular but are not that stringent. On the previous page, we showed pictures of ring bus and mesh arrangements. ![]()
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